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Ultralow Distortion Differential ADC Driver ADA4939-1/ADA4939-2
FEATURES
Extremely low harmonic distortion -102 dBc HD2 @ 10 MHz -83 dBc HD2 @ 70 MHz -77 dBc HD2 @ 100 MHz -101 dBc HD3 @ 10 MHz -97 dBc HD3 @ 70 MHz -91 dBc HD3 @ 100 MHz Low input voltage noise: 2.3 nV/Hz High speed -3 dB bandwidth of 1.4 GHz, G = 2 Slew rate: 6800 V/s, 25% to 75% Fast overdrive recovery of <1 ns 0.5 mV typical offset voltage Externally adjustable gain Stable for differential gains 2 Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Single-supply operation: 3.3 V to 5 V
FUNCTIONAL BLOCK DIAGRAMS
16 -VS 15 -VS 13 -VS
12 PD 11 -OUT 10 +OUT 9 VOCM
-FB 1 +IN 2 -IN 3 +FB 4
ADA4939-1
14 -VS +VS 7
+VS 8
+VS 5
Figure 1. ADA4939-1
+IN1 -FB1 -VS1 -VS1 PD1 -OUT1
-IN1 +FB1 +VS1 +VS1 -FB2 +IN2
1 2 3 4 5 6
24 23 22 21 20 19
+VS 6
ADA4939-2
18 17 16 15 14 13
+OUT1 VOCM1 -VS2 -VS2 PD2 -OUT2
-IN2 +FB2 +VS2 +VS2 VOCM2 +OUT2
7 8 9 10 11 12
07429-001
APPLICATIONS
ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers
-60 -65
Figure 2. ADA4939-2
VOUT, dm = 2V p-p HD2 HD3
HARMONIC DISTORTION (dBc)
-70 -75 -80 -85 -90 -95 -100 -105 1
GENERAL DESCRIPTION
The ADA4939 is a low noise, ultralow distortion, high speed differential amplifier. It is an ideal choice for driving high performance ADCs with resolutions up to 16 bits from dc to 100 MHz. The output common-mode voltage is user adjustable by means of an internal common-mode feedback loop, allowing the ADA4939 output to match the input of the ADC. The internal feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. With the ADA4939, differential gain configurations are easily realized with a simple external feedback network of four resistors that determine the closed-loop gain of the amplifier. The ADA4939 is fabricated using Analog Devices, Inc., proprietary silicon-germanium (SiGe), complementary bipolar process, enabling it to achieve very low levels of distortion with an input voltage noise of only 2.3 nV/Hz. The low dc offset and excellent dynamic performance of the ADA4939 make it well suited for a wide variety of data acquisition and signal processing applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
10 FREQUENCY (MHz)
100
Figure 3. Harmonic Distortion vs. Frequency
The ADA4939 is available in a Pb-free, 3 mm x 3 mm 16-lead LFCSP (ADA4939-1, single) or a Pb-free, 4 mm x 4 mm 24-lead LFCSP (ADA4939-2, dual). The pinout has been optimized to facilitate PCB layout and minimize distortion. The ADA4939-1 and the ADA4939-2 are specified to operate over the -40C to +105C temperature range; both operate on supplies between 3.3 V and 5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07429-021
-110
07429-002
ADA4939-1/ADA4939-2 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Operation ............................................................................... 3 3.3 V Operation ............................................................................ 5 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Maximum Power Dissipation ..................................................... 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Test Circuits..................................................................................... 15 Operational Description................................................................ 16 Definition of Terms.................................................................... 16 Theory of Operation ...................................................................... 17 Analyzing an Application Circuit ............................................ 17 Setting the Closed-Loop Gain .................................................. 17 Stable for Gains 2 ..................................................................... 17 Estimating the Output Noise Voltage ...................................... 17 Impact of Mismatches in the Feedback Networks................. 18 Calculating the Input Impedance for an Application Circuit ....................................................................................................... 19 Input Common-Mode Voltage Range ..................................... 21 Input and Output Capacitive AC-Coupling ........................... 21 Minimum RG Value of 50 ...................................................... 21 Setting the Output Common-Mode Voltage .......................... 21 Layout, Grounding, and Bypassing.............................................. 22 High Performance ADC Driving ................................................. 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
5/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADA4939-1/ADA4939-2 SPECIFICATIONS
5 V OPERATION
TA = 25C, +VS = 5 V, -VS = 0 V, VOCM = +VS/2, RF = 402 , RG = 200 , RT = 60.4 (when used), RL, dm = 1 k, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
DIN to VOUT, dm Performance
Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Conditions VOUT, dm = 0.1 V p-p VOUT, dm = 0.1 V p-p, ADA4939-1 VOUT, dm = 0.1 V p-p, ADA4939-2 VOUT, dm = 2 V p-p VOUT, dm = 2 V p-p, 25% to 75% VIN = 0 V to 1.5 V step, G = 3.16 See Figure 41 for distortion test circuit VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p f = 100 kHz f = 100 kHz f = 100 MHz, ADA4939-2 VOS, dm = VOUT, dm/2, VDIN+ = VDIN- = 2.5 V TMIN to TMAX variation TMIN to TMAX variation Input Offset Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error -11.2 Differential Common mode 1.1 VOUT, dm/VIN, cm, VIN, cm = 1 V Maximum VOUT; single-ended output, RF = RG = 10 k VOUT, cm/VOUT, dm, VOUT, dm = 1 V, 10 MHz, see Figure 40 for test circuit 0.9 100 -64 -83 -3.4 -26 Min Typ 1400 300 90 1400 6800 <1 -102 -83 -77 -101 -97 -91 -95 -89 2.3 6 -80 0.5 2.0 -10 0.5 +0.5 180 450 1 +2.8 +2.2 +11.2 Max Unit MHz MHz MHz MHz V/s ns dBc dBc dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz dB mV V/C A A/C A k k pF V dB V mA dB
Third Harmonic
IMD Voltage Noise (RTI) Input Current Noise Crosstalk INPUT CHARACTERISTICS Offset Voltage Input Bias Current
3.9 -77 4.1
Rev. 0 | Page 3 of 24
ADA4939-1/ADA4939-2
VOCM to VOUT, cm Performance
Table 2.
Parameter VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Conditions Min Typ 670 2500 7.5 1.3 8.3 -3.7 0.97 3.5 11.5 +3.7 -73 0.99 Max Unit MHz V/s nV/Hz V k mV dB V/V
VIN = 1.5 V to 3.5 V, 25% to 75% f = 100 kHz
VOS, cm = VOUT, cm, VDIN+ = VDIN- = +VS/2 VOUT, dm/VOCM, VOCM = 1 V VOUT, cm/VOCM, VOCM = 1 V
9.7 0.5 -90 0.98
General Performance
Table 3.
Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Conditions Min 3.0 35.1 TMIN to TMAX variation Powered down VOUT, dm/VS, VS = 1 V Powered down Enabled 0.26 Typ Max 5.25 37.7 0.38 -80 Unit V mA A/C mA dB V V ns ns A A +105 C
Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled OPERATING TEMPERATURE RANGE
36.5 16 0.32 -90 1 2 500 100 30 -200
PD = 5 V PD = 0 V -40
Rev. 0 | Page 4 of 24
ADA4939-1/ADA4939-2
3.3 V OPERATION
TA = 25C, +VS = 3.3 V, -VS = 0 V, VOCM = +VS/2, RF = 402 , RG = 200 , RT = 60.4 (when used), RL, dm = 1 k, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
DIN to VOUT, dm Performance
Table 4.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Conditions VOUT, dm = 0.1 V p-p VOUT, dm = 0.1 V p-p, ADA4939-1 VOUT, dm = 0.1 V p-p, ADA4939-2 VOUT, dm = 2 V p-p VOUT, dm = 2 V p-p, 25% to 75% VIN = 0 V to 1.0 V step, G = 3.16 See Figure 41 for distortion test circuit VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p f = 100 kHz f = 100 kHz f = 100 MHz, ADA4939-2 VOS, dm = VOUT, dm/2, VDIN+ = VDIN- = +VS/2 TMIN to TMAX variation TMIN to TMAX variation Input Offset Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error -11.2 Differential Common mode 0.9 VOUT, dm/VIN, cm, VIN, cm = 1 V Maximum VOUT, single-ended output, RF = RG = 10 k VOUT, cm/VOUT, dm, VOUT, dm = 1 V, f = 10 MHz, see Figure 40 for test circuit 0.8 75 -61 -85 -3.5 -26 Min Typ 1400 300 90 1400 5000 <1 -100 -90 -83 -94 -82 -75 -87 -70 2.3 6 -80 0.5 2.0 -10 0.5 0.4 180 450 1 +3.5 +2.2 +11.2 k k pF V dB V mA dB Max Unit MHz MHz MHz MHz V/s ns dBc dBc dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz dB mV V/C A A/C
Third Harmonic
IMD Voltage Noise (RTI) Input Current Noise Crosstalk INPUT CHARACTERISTICS Offset Voltage Input Bias Current
2.4 -75 2.5
Rev. 0 | Page 5 of 24
ADA4939-1/ADA4939-2
VOCM to VOUT, cm Performance
Table 5.
Parameter VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Conditions Min Typ 560 1250 7.5 1.3 8.3 -3.7 0.97 1.9 11.2 +3.7 -73 0.99 Max Unit MHz V/s nV/Hz V k mV dB V/V
VIN = 0.9 V to 2.4 V, 25% to 75% f = 100 kHz
VOS, cm = VOUT, cm, VDIN+ = VDIN- = 1.67 V VOUT, dm/VOCM, VOCM = 1 V VOUT, cm/VOCM, VOCM = 1 V
9.7 0.5 -75 0.98
General Performance
Table 6.
Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Conditions Min 3.0 32.8 TMIN to TMAX variation Powered down VOUT, dm/VS, VS = 1 V Powered down Enabled 0.16 Typ Max 5.25 36.0 0.26 -72 Unit V mA A/C mA dB V V ns ns A A +105 C
Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled OPERATING TEMPERATURE RANGE
34.5 16 0.20 -84 1 2 500 100 26 -137
PD = 3.3 V PD = 0 V -40
Rev. 0 | Page 6 of 24
ADA4939-1/ADA4939-2 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Supply Voltage Power Dissipation Input Current, +IN, -IN, PD Storage Temperature Range Operating Temperature Range ADA4939-1 ADA4939-2 Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 5.5 V See Figure 4 5 mA -65C to +125C -40C to +105C -40C to +105C 300C 150C
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead LFCSP (98C/W) and the dual 24-lead LFCSP (67C/W) on a JEDEC standard four-layer board with the exposed pad soldered to a PCB pad that is connected to a solid plane.
3.0
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
MAXIMUM POWER DISSIPATION (W)
JA is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in EIA/JESD 51-7. Table 8. Thermal Resistance
Package Type ADA4939-1, 16-Lead LFCSP (Exposed Pad) ADA4939-2, 24-Lead LFCSP (Exposed Pad) JA 98 67 Unit C/W C/W
2.5 ADA4939-2 2.0
1.5 ADA4939-1 1.0
0.5
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4939 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4939. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure.
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a Four-Layer Board
ESD CAUTION
Rev. 0 | Page 7 of 24
07429-004
0 -40
ADA4939-1/ADA4939-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 -VS 15 -VS 14 -VS 13 -VS
-FB 1 +IN 2 -IN 3 +FB 4
PIN 1 INDICATOR
12 PD 11 -OUT 10 +OUT 9 VOCM
07429-005
ADA4939-1
TOP VIEW (Not to Scale)
-IN1 +FB1 +VS1 +VS1 -FB2 +IN2
1 2 3 4 5 6
24 23 22 21 20 19
PIN 1 INDICATOR
+IN1 -FB1 -VS1 -VS1 PD1 -OUT1
ADA4939-2
TOP VIEW (Not to Scale)
18 17 16 15 14 13
+OUT1 VOCM1 -VS2 -VS2 PD2 -OUT2
+VS 7
+VS 5
+VS 6
+VS 8
-IN2 +FB2 +VS2 +VS2 VOCM2 +OUT2
7 8 9 10 11 12
Figure 5. ADA4939-1 Pin Configuration
Figure 6. ADA4939-2 Pin Configuration
Table 9. ADA4939-1 Pin Function Descriptions
Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 Mnemonic -FB +IN -IN +FB +VS VOCM +OUT -OUT PD -VS Description Negative Output for Feedback Component Connection Positive Input Summing Node Negative Input Summing Node Positive Output for Feedback Component Connection Positive Supply Voltage Output Common-Mode Voltage Positive Output for Load Connection Negative Output for Load Connection Power-Down Pin Negative Supply Voltage
Table 10. ADA4939-2 Pin Function Descriptions
Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 Mnemonic -IN1 +FB1 +VS1 -FB2 +IN2 -IN2 +FB2 +VS2 VOCM2 +OUT2 -OUT2 PD2 -VS2 VOCM1 +OUT1 -OUT1 PD1 -VS1 -FB1 +IN1 Description Negative Input Summing Node 1 Positive Output Feedback 1 Positive Supply Voltage 1 Negative Output Feedback 2 Positive Input Summing Node 2 Negative Input Summing Node 2 Positive Output Feedback 2 Positive Supply Voltage 2 Output Common-Mode Voltage 2 Positive Output 2 Negative Output 2 Power-Down Pin 2 Negative Supply Voltage 2 Output Common-Mode Voltage 1 Positive Output 1 Negative Output 1 Power-Down Pin 1 Negative Supply Voltage 1 Negative Output Feedback 1 Positive Input Summing Node 1
Rev. 0 | Page 8 of 24
07429-006
ADA4939-1/ADA4939-2 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, +VS = 5 V, -VS = 0 V, VOCM = +VS /2, RG = 200 , RF = 402 , RT = 60.4 , G = 1, RL, dm = 1 k, unless otherwise noted. Refer to Figure 39 for test setup. Refer to Figure 42 for signal definitions.
2 VOUT, dm = 100mV p-p 2 VOUT, dm = 2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -2 -4 -6 -8 -10 -12 -14 1 G = +2.00 G = +3.16 G = +5.00 10 RG = 200, RT = 60.4 RG = 127, RT = 66.3 RG = 80.6, RT = 76.8
07429-007
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -2 -4 -6 -8 -10 -12 -14 1 G = +2.00 G = +3.16 G = +5.00 10 RG = 200, RT = 60.4 RG = 127, RT = 66.3 RG = 80.6, RT = 76.8 100 FREQUENCY (MHz) 1k
07429-010 07429-012 07429-011
100 FREQUENCY (MHz)
1k
Figure 7. Small Signal Frequency Response for Various Gains
3 2
Figure 10. Large Signal Frequency Response for Various Gains
2
VOUT, dm = 100mV p-p
VOUT, dm = 2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 VS = 3.3V VS = 5.0V 10 100 FREQUENCY (MHz) 1k
07429-008
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -2 -4 -6 -8 -10 -12 1 VS = 3.3V VS = 5.0V 10 100 FREQUENCY (MHz) 1k
Figure 8. Small Signal Frequency Response for Various Supplies
3 2
Figure 11. Large Signal Frequency Response for Various Supplies
3 2
VOUT, dm = 100mV p-p
VOUT, dm = 2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 -40C +25C +105C
07429-009
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 -40C +25C +105C 10 100 FREQUENCY (MHz) 1k
10
100 FREQUENCY (MHz)
1k
Figure 9. Small Signal Frequency Response for Various Temperatures
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. 0 | Page 9 of 24
ADA4939-1/ADA4939-2
3 2 VOUT, dm = 100mV p-p 3 2 VOUT, dm = 2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 RL = 1k RL = 200
07429-013
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 RL = 1k RL = 200 10 100 FREQUENCY (MHz) 1k
07429-016
07429-023 07429-022
10
100 FREQUENCY (MHz)
1k
Figure 13. Small Signal Frequency Response for Various Loads
6
Figure 16. Large Signal Frequency Response for Various Loads
VOUT, dm = 100mV p-p
-55 -60
HARMONIC DISTORTION (dBc)
VOUT, dm = 2V p-p HD2, HD3, HD2, HD3, HD2, HD3, G G G G G G =2 =2 = 3.16 = 3.16 =5 =5
3
-65 -70 -75 -80 -85 -90 -95 -100 -105 -110
10 100 1k
07429-019
VOCM GAIN (dB)
0
-3
-6 VOCM = 1.0V VOCM = 3.9V VOCM = 2.5V 1 FREQUENCY (MHz)
-9
-115 1 10 FREQUENCY (MHz) 100
Figure 14. VOCM Small Signal Frequency Response at Various DC Levels
0.5
Figure 17. Harmonic Distortion vs. Frequency at Various Gains
-60 -65
VOUT, dm = 100mV p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
0.4
VOUT, dm = 2V p-p VS = 2.5V HD2, HD3, HD2, HD3, RL, dm = 1k RL, dm = 1k RL, dm = 200 RL, dm = 200
HARMONIC DISTORTION (dBc)
07429-020
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 RL = 1k RL = 200 RL = 1k OUT1 RL = 1k OUT2 RL = 200 OUT1 RL = 200 OUT2 10 100 1k FREQUENCY (MHz)
-70 -75 -80 -85 -90 -95 -100 -105 -110 1
10 FREQUENCY (MHz)
100
Figure 15. 0.1 dB Flatness Small Signal Response for Various Loads
Figure 18. Harmonic Distortion vs. Frequency at Various Loads
Rev. 0 | Page 10 of 24
ADA4939-1/ADA4939-2
-60 -65 VOUT, dm = 2V p-p HD2, HD3, HD2, HD3, VS (SPLIT VS (SPLIT VS (SPLIT VS (SPLIT SUPPLY) = 2.5V SUPPLY) = 2.5V SUPPLY) = 1.65V SUPPLY) = 1.65V
-40 -50 -60
HARMONIC DISTORTION (dBc)
-70 -75 -80 -85 -90 -95 -100 -105
DISTORTION (dBc)
-70 -80 -90 -100 -110 -120 HD2, HD3, HD2, HD3, 0 1 2 3 4 5 VS = 5.0 VS = 5.0 VS = 3.3 VS = 3.3 6 7
07429-024
07429-029 07429-028
1
10 FREQUENCY (MHz)
100
07429-062
-110
-130 VOUT, dm (V p-p)
Figure 19. Harmonic Distortion vs. Frequency at Various Supplies
-40 VOUT, dm = 2V p-p -50
Figure 22. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
10 0
NORMALIZED SPECTRUM (dBc)
VOUT, dm = 2V p-p VS = 2.5V
-60
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
DISTORTION (dBc)
-70 -80 -90 -100 -110 HD2, HD3, HD2, HD3, f = 10MHz f = 10MHz f = 70MHz f = 70MHz
07429-025
-120 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 VOCM (V)
-110 69.5
69.6
69.7
69.8
69.9
70.0
70.1
70.2
70.3
70.4
70.5
FREQUENCY (MHz)
Figure 20. Harmonic Distortion vs. VOCM at Various Frequencies
-40 VOUT, dm = 2V p-p -50 -60 -35 -40 -45 -50 -55 -60 HD2, HD3, HD2, HD3, 1.4 1.6 VOCM (V) 1.8 f = 10MHz f = 10MHz f = 70MHz f = 70MHz 2.0
07429-026
Figure 23. 70 MHz Intermodulation Distortion
-30
RL, dm = 200
DISTORTION (dBc)
-70 -80 -90 -100 -110 -120 -130 1.2
CMRR (dB)
-65 -70 1 10 100 1k FREQUENCY (MHz)
Figure 21. Harmonic Distortion vs. VOCM at Various Frequencies
Figure 24. CMRR vs. Frequency
Rev. 0 | Page 11 of 24
ADA4939-1/ADA4939-2
-60 VOUT, dm = HD2, VOUT, dm = HD3, VOUT, dm = HD2, VOUT, dm = HD3, = 1V p-p = 1V p-p = 2V p-p = 2V p-p VS = 1.65V
-30 -35 -40 -45 -50 -55 -60 -65 -70 1
RL, dm = 200
-70
HARMONIC DISTORTION (dBc)
-80
-90
-100
-110
07429-027
1
10 FREQUENCY (MHz)
100
10
100
1k
FREQUENCY (MHz)
Figure 25. Harmonic Distortion vs. Frequency at Various Output Voltages
-30 -40 -50
70 60 50 40
Figure 28. Output Balance vs. Frequency
100 GAIN 50 0
RL, dm = 200
GAIN (dB)
-60 -70 -80 -90 -100 1 10 100 1k FREQUENCY (MHz)
-100 30 -150 20 10 0 -10 0.01 -200 -250 -300
07429-031
0.1
1
10
100
1k
FREQUENCY (MHz)
Figure 26. PSRR vs. Frequency, RL = 200
8
RL, dm = 200
Figure 29. Open-Loop Gain and Phase vs. Frequency
0 -5 -10
6 4
S-PARAMETERS (dB)
-15 -20 S22 -25 -30 -35 -40 -45
07429-032
S11
VOLTAGE (V)
2 0 -2 -4 -6 VIN x 3.16V -8 0 10 20 30 TIME (ns) 40 50 60 VOUT
1
10
100 FREQUENCY (MHz)
1k
Figure 27. Return Loss (S11, S22) vs. Frequency
Figure 30. Overdrive Recovery, G = 3.16
Rev. 0 | Page 12 of 24
07429-035
-50
07429-034
-350 10k
PHASE (Degrees)
PHASE
-50
PSRR (dB)
07429-030
-120
OUTPUT BALANCE (dB)
ADA4939-1/ADA4939-2
-60
SPURIOUS-FREE DYNAMIC RANGE (dBc)
-65 -70
VOUT, dm = 2V p-p VS = 2.5V
-40 -50 -60
RL, dm = 200
RL = 200 -80 -85 RL = 1k -90 -95 -100
07429-033
CROSSTALK (dB)
-75
-70 -80 -90 -100 -110 -120 -130
INPUT AMP 1 TO OUTPUT AMP 2
INPUT AMP 2 TO OUTPUT AMP 1
1
10 FREQUENCY (MHz)
100
1
10
100
1k
FREQUENCY (MHz)
Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads
0.12 0.10 4 3 2 1 0 -1 -2 -3 -4 0
Figure 34. Crosstalk vs. Frequency for ADA4939-2
OUTPUT VOLTAGE (V)
0.06 0.04 0.02 0 -0.02 0 1 2 3 4 5 TIME (ns) 6 7 8 9 10
07429-038
OUTPUT VOLTAGE (V)
0.08
1
2
3
4
5 TIME (ns)
6
7
8
9
10
Figure 32. Small Signal Pulse Response
2.60 4.5
Figure 35. Large Signal Pulse Response
OUTPUT COMMON-MODE VOLTAGE (V)
OUTPUT COMMON-MODE VOLTAGE (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20
2.55
2.50
2.45
07429-039
0
2
4
6
8
10 TIME (ns)
12
14
16
18
20
Figure 33. VOCM Small Signal Pulse Response
Figure 36. VOCM Large Signal Pulse Response
Rev. 0 | Page 13 of 24
07429-042
2.40
07429-041
07429-044
-105
-140
ADA4939-1/ADA4939-2
3.5 RL, dm = 200 3.0 2.5 VOUT, dm 1k
INPUT VOLTAGE NOISE (nV/ Hz)
07429-043
VOLTAGE (V)
2.0 PD 1.5 1.0 0.5 0 -0.5 0 100 200 300 400 500 600 700 800 900 1000 TIME (ns)
100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 37. PD Response Time
Figure 38. Voltage Noise Spectral Density, RTI
Rev. 0 | Page 14 of 24
07429-045
1 10
ADA4939-1/ADA4939-2 TEST CIRCUITS
402 5V 50 VIN 0.1F 200 VOCM 200
07429-046
60.4
ADA4939
1k
0.1F 402
Figure 39. Equivalent Basic Test Circuit, G = 2
NETWORK ANALYZER OUTPUT AC-COUPLED 50 VIN 200 VOCM 200 0.1F 60.4
402 +2.5V
49.9 NETWORK ANALYZER INPUT AC-COUPLED
49.9
60.4
ADA4939
49.9
50
49.9
Figure 40. Test Circuit for Output Balance, CMRR
402 5V 50 VIN 0.1F 200 LOW-PASS FILTER 60.4 VOCM 200 0.1F 402 0.1F 442 200 2:1 50 DUAL FILTER
ADA4939
0.1F
261 442
CT
07429-047
-2.5V 402
Figure 41. Test Circuit for Distortion Measurements
Rev. 0 | Page 15 of 24
07429-048
ADA4939-1/ADA4939-2 OPERATIONAL DESCRIPTION
DEFINITION OF TERMS
-FB RG RF +IN -OUT
Common-Mode Voltage
Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as
RL, dm VOUT, dm
07429-049
+DIN VOCM -DIN +FB
ADA4939
RG R F -IN +OUT
VOUT, cm = (V+OUT + V-OUT)/2
Balance
Output balance is a measure of how close the differential signals are to being equal in amplitude and opposite in phase. Output balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see Figure 39). By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage.
Figure 42. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently, output differential-mode voltage) is defined as VOUT, dm = (V+OUT - V-OUT) where V+OUT and V-OUT refer to the voltages at the +OUT and -OUT terminals with respect to a common reference.
Output Balance Error =
VOUT , cm VOUT , dm
Rev. 0 | Page 16 of 24
ADA4939-1/ADA4939-2 THEORY OF OPERATION
The ADA4939 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions and an additional input, VOCM. Like an op amp, it relies on high openloop gain and negative feedback to force these outputs to the desired voltages. The ADA4939 behaves much like a standard voltage feedback op amp and facilitates single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. Like an op amp, the ADA4939 has high input impedance and low output impedance. Because it uses voltage feedback, the ADA4939 manifests a nominally constant gainbandwidth product. Two feedback loops are employed to control the differential and common-mode output voltages. The differential feedback, set with external resistors, controls only the differential output voltage. The common-mode feedback controls only the common-mode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. The output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the VOCM input. The internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. This results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180 apart in phase.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 42 can be determined by
VOUT , dm VIN , dm
=
RF RG
This presumes that the input resistors (RG) and feedback resistors (RF) on each side are equal.
STABLE FOR GAINS 2
The ADA4939 frequency response exhibits excessive peaking for differential gains <2; therefore, the part should be operated with differential gains 2.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4939 can be estimated using the noise model in Figure 43. The input-referred noise voltage density, vnIN, is modeled as a differential input, and the noise currents, inIN- and inIN+, appear between each input and ground. The output voltage due to vnIN is obtained by multiplying vnIN by the noise gain, GN (defined in the GN equation that follows). The noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. The noise voltage density at the VOCM pin is vnCM. When the feedback networks have the same feedback factor, as in most cases, the output noise due to vnCM is common-mode. Each of the four resistors contributes (4kTRxx)1/2. The noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by RF/RG. Table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms.
VnRG1 RG1 RF1 VnRF1
ANALYZING AN APPLICATION CIRCUIT
The ADA4939 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and -IN (see Figure 42). For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed.
inIN+ + inIN-
VnIN
ADA4939
VOCM
VnOD
VnRG2
RG2
RF2
VnRF2
Figure 43. Noise Model
Rev. 0 | Page 17 of 24
07429-050
VnCM
ADA4939-1/ADA4939-2
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor RG1 Gain Resistor RG2 Feedback Resistor RF1 Feedback Resistor RF2 Input Noise Term vnIN inIN inIN vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN x (RF2) inIN x (RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Output Multiplication Factor GN 1 1 0 RF1/RG1 RF2/RG2 1 1 Differential Output Noise Voltage Density Term vnO1 = GN(vnIN) vnO2 = (inIN)(RF2) vnO3 = (inIN)(RF1) vnO4 = 0 vnO5 = (RF1/RG1)(4kTRG1)1/2 vnO6 = (RF2/RG2)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB) 6 10 14 RF () 402 402 402 RG () 200 127 80.6 RIN, dm () 400 254 161 Differential Output Noise Density (nV/Hz) 9.7 12.4 16.6
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50
Nominal Gain (dB) 6 10 14
1
RF () 402 402 402
RG1 () 200 127 80.6
RT () 60.4 66.5 76.8
RIN, cm () 301 205 138
RG2 ()1 228 155 111
Differential Output Noise Density (nV/Hz) 9.1 11.1 13.5
RG2 = RG1 + (RS||RT).
Similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +IN and -IN by the appropriate output factor, where:
IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS
As previously mentioned, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remain equal and 180 out of phase. The input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. The gain from the VOCM pin to VO, dm is equal to 2(1 - 2)/(1 + 2) When 1 = 2, this term goes to zero and there is no differential output voltage due to the voltage on the VOCM input (including noise). The extreme case occurs when one loop is open and the other has 100% feedback; in this case, the gain from VOCM input to VO, dm is either +2 or -2, depending on which loop is closed. The feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the VOCM input are negligible. If the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from VOCM to VO, dm and account for the extra noise. For example, if 1 = 0.5 and 2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the VOCM pin is set to 2.5 V, a differential offset voltage is present at the output of (2.5 V)(0.67) = 1.67 V. The differential output noise contribution is (7.5 nV/Hz)(0.67) = 5 nV/Hz. Both of these results are undesirable in most applications; therefore, it is best to use nominally matched feedback factors.
GN =
(1 + 2 )
2
is the circuit noise gain.
1 =
RG1 RG2 and 2 = are the feedback factors. RF1 + RG1 RF2 + RG2
When the feedback factors are matched, RF1/RG1 = RF2/RG2, 1 = 2 = , and the noise gain becomes
GN =
1 R =1+ F RG
Note that the output noise from VOCM goes to zero in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. v nOD =
2 vnOi
i =1 8
Table 12 and Table 13 list several common gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations.
Rev. 0 | Page 18 of 24
ADA4939-1/ADA4939-2
Mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. As a practical summarization of the above issues, resistors of 1% tolerance produce a worst-case input CMRR of approximately 40 dB, a worst-case differential-mode output offset of 25 mV due to a 2.5 V VOCM input, negligible VOCM noise contribution, and no significant degradation in output balance error.
The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG. The common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider formed by RF and RG in the lower loop. This voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across RG in the upper loop and partially bootstrapping RG.
CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 44, the input impedance (RIN, dm) between the inputs (+DIN and -DIN) is simply RIN, dm = 2 x RG.
RF
Terminating a Single-Ended Input
This section deals with how to properly terminate a singleended input to the ADA4939 with a gain of 2, RF = 400 , and RG = 200 . An example using an input source with a terminated output voltage of 1 V p-p and source resistance of 50 illustrates the four simple steps that must be followed. Note that because the terminated output voltage of the source is 1 V p-p, the open circuit output voltage of the source is 2 V p-p. The source shown in Figure 46 indicates this open-circuit voltage. 1. The input impedance must be calculated using the formula
ADA4939
+VS +DIN -DIN RG +IN VOCM -IN RF VOUT, dm
07429-051
RG
Figure 44. ADA4939 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 45), the input impedance is
RG = RF 1- 2 x (RG + RF )
RF RIN, SE RG VOCM RG +VS
RG 200 = 300 = RIN = 400 RF 1- 1- 2 x (200 + 400) 2 x (RG + RF )
RF RIN 300 RS VS 2V p-p 50 RG 200 VOCM RG 200 -VS 400 +VS
RIN , SE
ADA4939
RL VOUT, dm
ADA4939
RL
VOUT, dm
400
Figure 46. Calculating Single-Ended Input Impedance RIN
RF
Figure 45. ADA4939 with Unbalanced (Single-Ended) Input
07429-052
-VS
Rev. 0 | Page 19 of 24
07429-053
RF
ADA4939-1/ADA4939-2
2. In order to match the 50 source resistance, the termination resistor, RT, is calculated using RT||300 = 50 . The closest standard 1% value for RT is 60.4 .
RF RIN 50 RS VS 2V p-p 50 RT 60.4 RG 200 VOCM RG 200 -VS RF 400
07429-054
400 +VS
ADA4939
RL
VOUT, dm
It is useful to point out two effects that occur with a terminated input. The first is that the value of RG is increased in both loops, lowering the overall closed-loop gain. The second is that VTH is a little larger than 1 V p-p, as it would be if RT = 50 . These two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 k), the effects essentially cancel each other out. For small RF and RG, however, the diminished closed-loop gain is not canceled completely by the increased VTH. This can be seen by evaluating Figure 49. The desired differential output in this example is 2 V p-p because the terminated input signal was 1 V p-p and the closed-loop gain = 2. The actual differential output voltage, however, is equal to (1.09 V p-p)(400/227.4) = 1.92 V p-p. To obtain the desired output voltage of 2 V p-p, a final gain adjustment can be made by increasing RF without modifying any of the input circuitry. This is discussed in Step 4. 4. The feedback resistor value is modified as a final gain adjustment to obtain the desired output voltage. To make the output voltage VOUT = 2 V p-p, RF must be calculated using the following formula:
RF =
Figure 47. Adding Termination Resistor RT
3.
It can be seen from Figure 47 that the effective RG in the upper feedback loop is now greater than the RG in the lower loop due to the addition of the termination resistors. To compensate for the imbalance of the gain resistors, a correction resistor (RTS) is added in series with RG in the lower loop. RTS is equal to the Thevenin equivalent of the source resistance RS and the termination resistance RT and is equal to RS||RT.
RS VS 2V p-p 50 RT 60.4 VTH 1.09V p-p RTH 27.4
07429-055
(Desired V
OUT ,dm
)(R
G
+ RTS )
VTH
=
(2VP -P )(227.4 ) = 417
1.09VP -P
Figure 48. Calculating the Thevenin Equivalent
The closest standard 1 % values to 417 are 412 and 422 . Choosing 422 gives a differential output voltage of 2.02 V p-p. The final circuit is shown in Figure 50.
RF 1V p-p RS VS 2V p-p 50 RT 60.4 RG 200 VOCM RG 422 +VS
RTS = RTH = RS||RT = 27.4 . Note that VTH is greater than 1 V p-p, which was obtained with RT = 50 . The modified circuit with the Thevenin equivalent of the terminated source and RTS in the lower feedback loop is shown in Figure 49.
RF 400 +VS RTH VTH 1.09V p-p 27.4 RG 200 VOCM RG RTS 27.4 200 -VS RF 400
ADA4939
RL
VOUT, dm 2.02V p-p
ADA4939
RL VOUT, dm
RTS 27.4
200
07429-057
-VS RF 422
07429-056
Figure 50. Terminated Single-Ended-to-Differential System with G = 2
Figure 49. Thevenin Equivalent and Matched Gain Resistors
Figure 49 presents a tractable circuit with matched feedback loops that can be easily evaluated.
Rev. 0 | Page 20 of 24
ADA4939-1/ADA4939-2
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4939 input common-mode range is centered between the two supply rails, in contrast to other ADC drivers with level-shifted input ranges, such as the ADA4937. The centered input commonmode range is best suited to ac-coupled, differential-to-differential and dual supply applications. For 5 V single-supply operation, the input common-mode range at the summing nodes of the amplifier is specified as 1.1 V to 3.9 V and is specified as 0.9 V to 2.4 V with a 3.3 V supply. To avoid nonlinearities, the voltage swing at the +IN and -IN terminals must be confined to these ranges.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4939 is internally biased with a voltage divider comprising two 20 k resistors at a voltage approximately equal to the midsupply point, [(+VS) + (-VS)]/2. Because of this internal divider, the VOCM pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. Relying on the internal bias results in an output common-mode voltage that is within about 100 mV of the expected value. In cases where more accurate control of the output commonmode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 . The output common-mode offset listed in the Specifications section assumes that the VOCM input is driven by a low impedance voltage source. It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC. However, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 10 k. If multiple ADA4939 devices share one reference output, it is recommended that a buffer be used.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Input ac coupling capacitors can be inserted between the source and RG. This ac coupling blocks the flow of the dc commonmode feedback current and causes the ADA4939 dc input common-mode voltage to equal the dc output common-mode voltage. These ac coupling capacitors must be placed in both loops to keep the feedback factors matched. Output ac coupling capacitors can be placed in series between each output and its respective load. See Figure 54 for an example that uses input and output capacitive ac coupling.
MINIMUM RG VALUE OF 50
Due to the wide bandwidth of the ADA4939, the value of RG must be greater than or equal to 50 to provide sufficient damping in the amplifier front end. In the terminated case, RG includes the Thevenin resistance of the source and load terminations.
Rev. 0 | Page 21 of 24
ADA4939-1/ADA4939-2 LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4939 is sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. This section shows a detailed example of how the ADA4939-1 was addressed. The first requirement is a solid ground plane that covers as much of the board area around the ADA4939-1 as possible. However, the area near the feedback resistors (RF), gain resistors (RG), and the input summing nodes (Pin 2 and Pin 3) should be cleared of all ground and power planes (see Figure 51). Clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. The thermal resistance, JA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity four-layer circuit board, as described in EIA/JESD 51-7. The power supply pins should be bypassed as close to the device as possible and directly to a nearby ground plane. High frequency ceramic chip capacitors should be used. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 F) be used for each supply. The 1000 pF capacitor should be placed closer to the device. Further away, low frequency bypassing should be provided, using 10 F tantalum capacitors from each supply to ground. Signal routing should be short and direct to avoid parasitic effects. Wherever complementary signals exist, a symmetrical layout should be provided to maximize balanced performance. When routing differential signals over a long distance, PCB traces should be close together, and any differential wiring should be twisted such that loop area is minimized. Doing this reduces radiated energy and makes the circuit less susceptible to interference.
1.30 0.80
1.30 0.80
07429-058
Figure 51. Ground and Power Plane Voiding in Vicinity of RF and RG
Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
1.30 TOP METAL
GROUND PLANE
0.30
PLATED VIA HOLE
POWER PLANE
07429-060
BOTTOM METAL
Figure 53. Cross-Section of Four-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Rev. 0 | Page 22 of 24
07429-059
ADA4939-1/ADA4939-2 HIGH PERFORMANCE ADC DRIVING
The ADA4939 is ideally suited for broadband ac-coupled and differential-to-differential applications on a single supply. The circuit in Figure 54 shows a front-end connection for an ADA4939 driving an AD9445, 14-bit, 105 MSPS ADC, with ac coupling on the ADA4939 input and output. (The AD9445 achieves its optimum performance when driven differentially.) The ADA4939 eliminates the need for a transformer to drive the ADC and performs a single-ended-to-differential conversion and buffering of the driving signal. The ADA4939 is configured with a single 5 V supply and gain of 2 for a single-ended input to differential output. The 60.4 termination resistor, in parallel with the single-ended input impedance of approximately 300 , provides a 50 termination for the source. The additional 27.4 (227.4 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. In this example, the signal generator has a 1 V p-p symmetric, ground-referenced bipolar output when terminated in 50 . The VOCM pin of the ADA4939 is bypassed for noise reduction and left floating such that the internal divider sets the output common-mode voltage nominally at midsupply. Because the inputs are ac-coupled, no dc common-mode current flows in the feedback loops, and a nominal dc level of midsupply is present at the amplifier input terminals. Besides placing the amplifier inputs at their optimum levels, the ac coupling technique lightens the load on the amplifier and dissipates less power than applications with dc-coupled inputs. With an output commonmode voltage of nominally 2.5 V, each ADA4937 output swings between 2.0 V and 3.0 V, providing a gain of 2 and a 2 V p-p differential signal to the ADC input. The output of the amplifier is ac-coupled to the ADC through a second-order, low-pass filter with a cutoff frequency of 100 MHz. This reduces the noise bandwidth of the amplifier and isolates the driver outputs from the ADC inputs. The AD9445 is configured for a 2 V p-p full-scale input by connecting the SENSE pin to AGND, as shown in Figure 54.
412 5V 50 0.1F 60.4 SIGNAL GENERATOR 200 VOCM 200 0.1F 0.1F 27.4 412 0.1F 0.1F 5V (A) 3.3V (A) 3.3V (D)
+
30nH 24.3
AVDD2 AVDD1 DRVDD VIN- BUFFER T/H 47pF ADC 14
AD9445
ADA4939
24.3 30nH VIN+ CLOCK/ TIMING AGND
REF SENSE
07429-061
Figure 54. ADA4939 Driving an AD9445 ADC with AC-Coupled Input and Output
Rev. 0 | Page 23 of 24
ADA4939-1/ADA4939-2 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF
9 8
0.60 MAX
0.50 0.40 0.30
PIN 1 INDICATOR *1.45 1.30 SQ 1.15
13 12
EXPOSED PAD
16
1
(BOTTOM VIEW) 4
5
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters
4.00 BSC SQ
0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30
19 18 EXPOSED PAD
(BOTTOM VIEW)
PIN 1 INDICATOR
24 1
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
2.25 2.10 SQ 1.95
7 6
13 12
0.25 MIN 2.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADA4939-1YCPZ-R2 1 ADA4939-1YCPZ-RL1 ADA4939-1YCPZ-R71 ADA4939-2YCPZ-R21 ADA4939-2YCPZ-RL1 ADA4939-2YCPZ-R71
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ
Package Option CP-16-2 CP-16-2 CP-16-2 CP-24-1 CP-24-1 CP-24-1
Ordering Quantity 250 5,000 1,500 250 5,000 1,500
Branding H1E H1E H1E
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07429-0-5/08(0)
Rev. 0 | Page 24 of 24

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